1. Field of the Invention
This invention relates to a high speed ECL gate circuit and, more particularly, relates to a dynamic ECL gate circuit for driving line loads having significant capacitance.
2. Discussion of Background and Prior Art
A form of current steering logic, known as emitter-coupled logic (ECL) is widely utilized. ECL results in high performance products and has the shortest propagation delay of any logic form. With ECL logic, superior comparator functions and high-speed analog-to-digital conversion may be accomplished. ECL logic is utilized in such diverse applications as instrumentation, computers, phased-array radar, telecommunication systems, and a host of modern electronics applications where high performance is required or desired.
Basic circuit design and processing for ECL is well known. See, e.g., Integrated Circuits: Design Principles and Fabrication, R. N. Warner, Jr., ed. McGraw-Hill (1965), Sec. 5-10, pp. 156-159. The most common ECL design is a multiple input OR/NOR gate. Such a gate is a versatile logic building block since it has complementary outputs. However, even though such ECL gates have an inherently low gate propagation delay, they have relatively slow rise and fall times. In addition, the gate propagation delay will be impacted with heavy capacitive loading; as shown in FIG. 6, for conventional ECL, as the load capacitance of the output lines increases, the propagation delay time increases linearly. While ECL circuitry has been shrunk and dense ECL-based logic arrays are self-contained on chip, the advent of very large scale integration (VLSI) has resulted in ECL circuitry in which the cumulative length of metal lines is large, on the order of 7 mm or more for a statistically significant number of devices. This results in capacitive loading of up to 1-10 pF, which is significant for individual ECL gates. See, e.g., A. H. Dansky, "Halving Load Resistances Shortens Long Path Delays", Electronics, Oct. 9, 1980, p. 146. This problem pertains also to ECL gate designs since they are based on the same circuit principles. See W. C. Seelbach, "Emitter Coupled Logic", Chp. 3 in Integrated Circuits Applications Handbook (Wiley 1983). As a consequence, the inherent speed advantage of ECL, which usually produces industry standard high performance products, disappears with significant capacitive loading.
One attempt to overcome the capacitive loading problem for ECL gates has been to utilize active pulldown transistors which bring down the line voltage at appropriate times in the logic cycle. This approach requires the generation of a separate pulldown reference voltage and does not produce energy efficient operation. See J. E. Price, "Emitter Coupled Logic Circuit With Active Pull-Down", U.S. Pat. No. 4,347,446. Such push-pull arrangements are difficult to design and require extra power supplies.
Another approach has been to couple the bases of output transistors through a resistor to complementary logic levels to increase high-to-low transition times. See, e.g., A. W. Chang et al, "Complementary Driver for Emitter-Coupled-Logic Gates", IBM Technical Disclosure Bulletin, v. 19, May, 1977, p. 4614; and M. Cases et al, "Emitter-Coupled Logic Totem-Pole Driver with Multiple Wired Logic Function Capability", IBM Technical Disclosure Bulletin, v. 20, February, 1978, p. 3471. This approach involves a continuous consumption of DC power through the resistors, is energy inefficient and is difficult to design.
It is therefore an object of the present invention to provide an ECL gate circuit which is capable of driving significant capacitive loads.
It is another object of the present invention to provide an ECL gate circuit which utilizes on-chip capacitances to speed up the pull-down of the output transitions.
It is another object of the present invention to utilize a complementary logic level within an ECL gate to speed up transitions by generating a voltage transient of appropriate sign on the base of the current source transistor connected to the logic output.